Technical Field
The embodiments herein generally relate to CMOS flip-flops. The embodiments herein more particularly relates to improving performance of the CMOS flip-flop in a metastable state.
Description of Related Art
In flip-flop circuitry, a signal has to assume one of two logic values (either logic ‘0’ or logic ‘1’) in order to be processed correctly. A common problem in such circuitry is that, the flip-flops are often unavoidably given ambiguous control signals which lead to a state known as ‘Metastability’. Metastability is a phenomenon that causes system failure, when a signal is transferred between circuitry in asynchronous clock domains. In metastable state, behavior of the flip-flop is unpredictable because outputs of the flip-flop assume values between logic 0 and 1, for an unusually longer period. As a result, the flip-flop acts in unpredictable ways and leads to ambiguous circuit states and erroneous data processing.
Moreover, metastable states are inherent features of flip-flops and cannot be completely avoided. The increasing expectations for reliable system operation make the prevention of metastability a basic consideration in flip-flops. There are several considerations, in practice, through which the effect of metastability is avoided. For example, one attempt to mitigate problem of metastable outputs in D flip-flop is to provide a second flip-flop in series with a first flip-flop (also known as ‘dual flip-flop arrangement’). This arrangement makes an asynchronous input given to the D flip-flop to a synchronized input. The arrangement further prevents setup/hold time violations and makes Mean Time between Failure (MTBF) rates of a D flip-flop larger. In another consideration, the metastable behavior is reduced by identifying setup and hold timings of the flip-flop and giving localized energy during, the setup/hold timing, violations to bring outputs to known stable states.
However, in the dual flip-flop arrangement, delay from input-to-valid output is more as it includes the delay through each of the D flip-flops, plus the delay between clocks to the D flip-flops. Furthermore, the logic fails if the output of the first D flip-flop remains in the metastable region for a period greater than the delay between the clocks.
Hence there is a need for a simple circuitry to reduce metastability in the flip-flops and make the outputs to go into known stable states within a lesser time.
The above mentioned shortcomings, disadvantages and problems are addressed herein and which will be understood by reading and studying the following specification.